Exclusive access transactions are used to prevent race conditions in multi-threaded applications. In the Advanced Reduced Instruction Set Computer (RISC) Machines (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced Extensible Interface (AXI) protocol, “exclusive load” and “exclusive store” transactions are types of exclusive access transactions. Each transaction, exclusive or non-exclusive, includes an AXI transaction identifier (ID) that identifies the master circuit as the source of the transaction. The AXI ID is also used to manage exclusive access to a referenced address(es).
The AXI transaction ID is also used by interconnect circuitry between master circuits and slave circuits for routing responses from the slave circuits to the master circuits. In complex interconnect circuits, which can include buses, switches, and bridges, for example, the AXI ID can be changed by the interconnect circuitry and cause problems in controlling exclusive access. For example, a system having 16 master circuits may require only 4 bits to uniquely identify the master circuits in an AXI ID. Depending on the complexity of the interconnect circuitry, the actual AXI ID may be much larger, for example, 12 bits. The large AXI word size is costly and not scalable to larger systems and complex interconnect topologies. In some implementations the large AXI ID is compressed, which in many cases leads to improper transport of exclusive access transactions.